Re: [PATCH/RFC] fix missing tlb flush on x86 smp+pae

["Stephen C. Tweedie" <sct@redhat.com>]

Hi,

On Fri, Mar 16, 2001 at 02:12:34PM +0100, Jamie Lokier wrote:
> Ben LaHaise wrote:
> > Below is a patch for 2.4 (it's against 2.4.2-ac20) that fixes a case where
> > pmd_alloc could install a new entry without causing a tlb flush on other
> > CPUs.  This was fatal with PAE because the CPU caches the top level of the
> > page tables, which was showing up as an infinite stream of identical page
> > faults.
> 
> Ew.  Is this the only case where adding a new entry requires a tlb
> flush?  It is quite an unusual requirement.

On Intel, yes.  The PAE case is a special case: we lose one bit of
addressing for each level of page table because the pte width has
doubled, so the two-level page table is short of two bits of address
coverage in PAE mode.  The CPU solves this by implementing a third
level page table, but it's just a tiny four-entry table, and because
it is so small the CPU just caches the whole pgd internally.

So, updating the pgd contents in this special case requires a tlb
flush because it's the only case where the CPU is caching the contents
of page tables other than the leaf pte entries.

Fortunately, the pgd being so tiny also implies that we hardly ever
need to add new entries: we can only ever do so three times per
process, and exec will almost always populate it fully before it is
finished as we load the binary into the first pmd, the libraries into
the second and the stack into the third (the fourth is the kernel
address space).

--Stephen
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