Re: Hello

["Stephen C. Tweedie" <sct@redhat.com>]

Hi,

On Sat, 1 May 1999 15:56:46 +0200, "Manfred Spraul"
<manfreds@colorfullife.com> said:

> Do you have any details about PSE-36?

Yes, the PDF docsets on Intel's developer pages cover it pretty well.

> This seems to be a page table extention for the Xeon CPU's
> AFAIK, this is not identical to PAE (available since PPro).

There are two separate extensions.  Since PPro, the CPUs have
supported large page tables.  Currently these can address 36 bits of
physical memory, but given that you have to deal with it in 4MB or 2MB
chunks, it is much less convenient than normal addressing and cannot
easily be used to support transparently the existing kernel
behaviour. 

The newer addressing mode is the 3-level page tables available in
PIIIs (and in later stepping PIIs, I think), which allow transparent
access to all of physical memory up to 64G.  That's what I'm aiming
for.

--Stephen
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