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Re: Lazy page reclamation on SMP machines: memory barriers

To: sct@dcs.ed.ac.uk
Subject: Re: Lazy page reclamation on SMP machines: memory barriers
From: "David S. Miller" <davem@dm.cobaltmicro.com>
Date: Tue, 24 Mar 1998 15:45:21 -0800
CC: torvalds@transmeta.com, sct@dcs.ed.ac.uk, linux-mm@kvack.org, linux-smp@vger.rutgers.edu
In-reply-to: <199803242254.WAA03274@dax.dcs.ed.ac.uk> (sct@dcs.ed.ac.uk)
References: <199803232249.WAA02431@dax.dcs.ed.ac.uk><Pine.LNX.3.95.980323151332.431D-100000@penguin.transmeta.com> <199803242254.WAA03274@dax.dcs.ed.ac.uk>
Sender: owner-linux-mm@kvack.org

   Date: 	Tue, 24 Mar 1998 22:54:18 GMT
   From: "Stephen C. Tweedie" <sct@dcs.ed.ac.uk>

   > Intel guarantees total ordering around any locked instruction, so
   > the spinlocks themselves act as the barriers. 

   Fine.  Can we assume that spinlocks and atomic set/clear_bit
   instructions have the same semantics on other CPUs?

Yes, you certainly can for spinlocks.

Later,
David S. Miller
davem@dm.cobaltmicro.com

References:
- Lazy page reclamation on SMP machines: memory barriers
  - From: "Stephen C. Tweedie" <sct@dcs.ed.ac.uk>
- Re: Lazy page reclamation on SMP machines: memory barriers
  - From: Linus Torvalds <torvalds@transmeta.com>
- Re: Lazy page reclamation on SMP machines: memory barriers
  - From: "Stephen C. Tweedie" <sct@dcs.ed.ac.uk>
- Re: Lazy page reclamation on SMP machines: memory barriers
  - From: "Stephen C. Tweedie" <sct@dcs.ed.ac.uk>

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