Re: smp and cache

[Momchil Velikov <velco@fadata.bg>]

>>>>> "Nir" == Nir Tzachar <tzachar@cs.bgu.ac.il> writes:

    >> *Especially* when it is not shared.
    >> 
    >> It is needed to allocate data to different cache lines, so logically
    >> independent accesses by different CPUs do not cause the cache line to
    >> bounce back and forth between CPUs.

    Nir> i get ur answer, but i think my problem is more fundamental:
    Nir> what do you (the kernel...) refer to when u speak of a "cache line" ??
    Nir> thanks...

A cache is collection of lines like:

[tag0] [byte0][byte1] ... [byteN]
[tag1] [byte0][byte1] ... [byteN]
[tag2] [byte0][byte1] ... [byteN]
[tag3] [byte0][byte1] ... [byteN]
  .       .      .    ...    .
[tagM] [byte0][byte1] ... [byteN]

where [tagK] is the cache line tag (physical address[1]) and [byteK]
is actual data.

  Note that there are different ways for map memory addresses to cache
lines. Search for "{direct-mapped, associative, set-associative}
cache".

  Cache line is also used as a shortcut for a cache-line size aligned
block in memory.

~velco

[1] Some idiotic designs have virtually indexed caches too.
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