Re: smp and cache

[Momchil Velikov <velco@fadata.bg>]

>>>>> "Nir" == Nir Tzachar <tzachar@cs.bgu.ac.il> writes:

Nir> hi all
Nir> i have a simple question, a bit hardware related: (intel/amd smp machines)
Nir> i know each cpu has an on-chip cache, but there are several cache
Nir> levels, so does each cpu has several levels or some of the levels are
Nir> shared among cpu's ???

Some of the common combinations are:

I.  [CPU] <-> [L1] <-> [L2] <-> [BUS]

II. [CPU] <-> [L1] <-> [L2] <-> [BUS] <-> [L2] <-> [L1] <-> [CPU]

III. [[CPU] <-> [L1] <-> [L2]] <-> [BUS] <-> [[L2] <-> [L1] <-> [CPU]]
     [                    ^  ]               [  ^                    ]
     [                    |  ]               [  |                    ]
     [[CPU] <-> [L1] <----+  ]               [  +----> [L1] <-> [CPU]]

Nir> if the cache is not shred, why is there still need to align cpu's specific
Nir> data of different cpus to different cache lines??

  *Especially* when it is not shared.

  It is needed to allocate data to different cache lines, so logically
independent accesses by different CPUs do not cause the cache line to
bounce back and forth between CPUs.

~velco
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